CD3215 Bootup Sequence
Getting 20V on the charger
If a CD3215 does not have the LDO outputs, test the lines for shorts, otherwise the chip is missing power or bad.
Data sheet of closest Ti chip.
A bad CD3215 can often cause a loop at step 10. All of the CD3215s need to be fully functional and communicate with the SMC before the CD3215 connected to the charger will request 20V.
The TBT ROM is required to get to 20V. It is powered by the CD3215 on the opposite side. It will not boot unless it can communicate. It seems with liquid in that area, the trace between the LDO of the CD3215 and TBT ROM gets damaged at the test point.
Please note, the chip designations and net names are from an A1706.
| Step | Source | Name of Net | Voltage |
| 1 | J3300 | PP20V_USBC_XB_VBUS | 5V |
| 2 | U3200 | PP3V3_UPC_XB_LDO | 3.3V |
| PP1V8_UPC_XB_LDOA | 1.8V | ||
| PP1V8_UPC_XB_LDOD | 1.8V | ||
| PP1V1_UPC_XB_BMC | 1.1V | ||
| 3 | U3200 | HV_GATE1 | High(5v, later 20V) |
| U3200 | HV_GATE2 | High(5v, later 20V) | |
| 4 | Q3200 | PPDCIN_G3H | 5V |
| 5 | U7000 | TBA_VDDA | 5V |
| 6 | U7000 | PM_EN_P3V3_G3H | 3.3V (5V on many boards) |
| 7 | U6903 | PP3V3_G3H | 3.3V |
| 8 | U5000 | PP1V2_G3H_SMC_VDDC | 1.2V |
| 9 | U5165 | PP3V0_G3H_AVREF_SMC | 3.0V |
| 10 | U5000 | SMBUS_SMC_4_G3H_SCL | 3.3V (clock) |
| U5000 | SMBUS_SMC_4_G3H_SDA | 3.3V (data) | |
| 11 | U3200 | USB_XB_CC1 | 0.8V (data) (verify) |
| U3200 | USB_XB_CC2 | 0.8V (data) (verify) | |
| 12 | J3300 | PP20V_USBC_XB_VBUS | 20V |
| J3300 | PP20V_USBC_XB_VBUS | 20V | |
| 13 | J3300 | HV_GATE1 | >20V |
| J3300 | HV_GATE2 | >20V | |
| 14 | Q3200 | PPDCIN_G3H | 20V |
| 15 | R7015 | TBA_AUX_DET | 5V |
| 16 | U7000 | SMC_RST_L | 3.3 (verify) |
| 17 | U7000 | Q7030 Q7040 opening | Unknown (low maybe) |
Booting fully
Thunderbolt isnt required to get 20V.
If you get a message saying Critical Update Required there may be a problem with the logic board.
