CD3215 Bootup Sequence
If a CD3215 does not have the LDO outputs, test the lines for shorts, otherwise the chip is missing power or bad. Data sheet of closest Ti chip.
A bad CD3215 can often cause a loop at step 10. All of the CD3215s need to be fully functional and communicate with the SMC before the CD3215 connected to the charger will request 20V.
The TBT ROM is required to get to 20V. It is powered by the CD3215 on the opposite side. It will not boot unless it can communicate. It seems with liquid in that area, the trace between the LDO of the CD3215 and TBT ROM gets damaged at the test point. Without communication with the TBT ROM, the 1.1V BMC LDO (PIN 35) won't come up while other LDOs will be present. The 1.1V BMC LDO is used to drive the logic negotiating USB-PD (USB 2.0 communications to charger). When that happens, when USB-C is connected to this CD3215, it will not negotiate 20V and get stuck on 5V, not cycling.
When one CD3215 in the system is bad, it will often cause others to not work as well, and they will often be power cycling after starting USB-PD negotiation as a result.
The CD3215 in one pair work in a master-slave fashion. For example on 820-00281, U3200 is the master while U3100 is the slave. The master is connected directly to the TBT ROM (U2890), while the slave (U3100) reads the TBT ROM firmware through the master (U3200). As a result, if the master (U3200) is not working properly, the slave (U3100) won't work either.
If all ports in all orientations are stuck at 5V, not power cycling, 1.1V BMC LDOs are good and the CC1/CC2 show good diode mode measurements, then there is probably an issue related to the communication between SMC and the USB-C controllers. Make sure to check that SMC_RESET_L and SMC_USBC_INT_L are properly pulled up to 3.3V.
Please note, the chip designations and net names are from an A1706.
|Step||Source||Name of Net||Voltage|
|3||U3200||HV_GATE1||High(5v, later 20V)(Air 10v, later 20V)|
|U3200||HV_GATE2||High(5v, later 20V)(Air 7.8v, later 20V)|
|6||U7000||PM_EN_P3V3_G3H (NC_CHGR_EN_VR1)||3.3V (5V on many boards)|
|8||U5000||PP1V2_G3H_SMC_VDDC or PP1V2_S5_SMC_VDDC||1.2V|
|9||U5165||PP3V0_G3H_AVREF_SMC or PP3V0_S5_AVREF_SMC||3.0V|
|11||U3200||USB_XB_CC1 (USBC_XB_CC1)||0.8V (data) (verify)|
|U3200||USB_XB_CC2 (USBC_XB_CC2)||0.8V (data) (verify)|
|17||U7000||Q7030 Q7040 opening||Unknown (low maybe)|
Thunderbolt ROM is required to get 20V.
If you get a message saying Critical Update Required there may be a problem with the logic board.
piernov 11.8.2020 at 9:29 AM
@ChrisB [VA, US] U3100/U3200 were 5V not cycling. U3200 was missing 1.1V BMC LDO. U3100 is missing it too, however it's the slave so it gets the TBT firmware through U3200 so that's normal. (I'm not sure if the slave could cause the master to have missing 1.1V BMC LDO though) At one point U3200 3.3V LDO was sending out 4.2V, so that was going to the TBT ROM (U2890) as well, I doubt it damaged it but it's a possibility. UB300 and UB400 were power cycling with 1.1V BMC LDO present, so they seem to be working fine, cycling being caused by the other pair.
→ Bad TBT ROM U2890 (1:24:00)
Issue: 820-00840 wont take anything from charger, either port, or orientation.
Visible inspection resulted in marks on CC1/2 pins on both USB-C ports.
Diode mode measurement showed ~0.550V on 3 of them, one ~0.040V.
Replacing the port fixed the issue.
Conclusion: One damaged CC pin can cause the whole lot to stop functioning.
820-00840 and 820-00875: U3100/U3200 were 5V not cycling. All LDO voltages were present. If battery is connected goes to 20V but 0mA and PPDCIN_G3H is 0V because Q32100/Q3200 closed due to 0v on UPC_XA_GATE1/UPC_XB_GATE1 . SMBUS_SMC_4_G3_SCL and SMBUS_SMC_4_G3_SDA at Step10 were 3.42V without any pull down, i.e. no communication between SMC and U3100/U3200. Resolved by reflowing SMC chip on 820-00875 and SMC replacement in case of 820-00840. Conclusion: communication between SMC and U3100/U3200 should be checked at Step10 by using oscilloscope.